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video_compression_systems
- 根据jpeg标准用verilog语言编写的视频编码器，此编码器可作为一个通用IP使用，完成数字音频/视频的编解码功能-under jpeg standards with the Verilog language video encoder, this encoder can be used as a common IP use, complete digital audio / video codec
DE2_TV
- 一个模拟视频输入转VGA视频输出的Verilog程序，视频解码芯片采用ADV7181B，VGA DAC采用ADV7123，强力推荐-an analog video input to VGA video output Verilog procedures, Video decoder chip used ADV7181B, VGA DAC used ADV7123, strongly recommended!
cmos_FPGA
- 采用Verilog语言,实现了FPGA控制视频芯片的数据采集,并将数据按帧存储起来-Verilog language, to achieve control of the FPGA chip video data acquisition, Data will be stored up by frame
在de2FPGA开发板上实现视频的采集
- 在de2FPGA开发板上实现视频的采集，以及播放~~verilog代码 希望对大家有所帮助,CCD to capture video sent to SDRAM LCM to controller LCD LCD to display the picture~
PAL
- PAL_D电视信号VHDL以及verilog源程序！ FPGA设计PAL_D电视信号！VHDL源程序！两个程序都是黑白的video信号，输出可以直接在视频显示器上显示。 -PAL_D TV signal VHDL and Verilog source!
mccd_capture
- 采用verilog语言，实现视频的采集。通过fpga控制，实现视频逐行采集。-The use of Verilog language, the implementation of video acquisition. Through the FPGA control, achieve progressive video collection.
RGMII_video_shiftregs
- 通过verilog编程，实现利用rgmii接口进行高速视频信号传输。-By verilog programming, high-speed video using rgmii interface signal transmission.
pong2
- fpga starter video game pong2 in verilog
giaotiepnt
- an analog video input to VGA video output Verilog
LIP6421CORE_video_decoder
- Video decoder verilog source code
RGB2YCbCr
- 视频格式空间转换 verilog语言实现-Space conversion video format verilog language
VHDL_Elimination-of-key-jitter
- 基于VHDL语言下的消除键抖动程序设计，很简单易懂的-Elimination of key jitter
color_bar
- 使用verilog编写的模块，输出1080p彩条测试视频，输入时钟频率可以为74.25M或者148.5M(The use of Verilog module, 1080p color video output test, input clock frequency is 74.25M or 148.5M)
display
- cbvs视频格式，驱动ADV7123,。。。。。。。。。。(Cbvs video format, drive ADV7123,..........)
code_cover_on_black_level_test_project1
- 视频处理的黑电平校正模块的代码覆盖率测试所用的TB(The TB for the code coverage test of the video processing black level correction module)
OV7670_TFT
- 针对OV7670视频采集和加水印功能，能够在显示屏上输出摄像头的画面并在画面任意位置添加水印(OV7670 video capture and watermark function)
CH14_RGMII_UDP_TEST
- 用xilinx的SPARTAN6 实现的UDP，可通过PC机网络抓包工具进行发送和接收，增加了网络视频传输的接口，具有很好的参考价值(With the Xilinx implementation of the SPARTAN6 UDP, can be sent and received through PC network capture tools, increase the network video transmission interface, has a good reference
Lesson07：BJ-EPM240学习板实验1——分频计数实验
- Quartus的分频计数试验视频讲解,讲解的很详细，对于新手来说还是蛮不错的(Quartus_frequency division technology test video explanation)
Lesson09：BJ-EPM240学习板实验2——按键消抖实验
- Quartus的按键消抖设计实验视频讲解,讲解的很详细，对于新手来说还是蛮不错的(Quartus key to shake down the design of experimental video explanation)
buffer
- Hi iam Ramana a research scholar,doing my phd from sathyabama university. Title: Designa video codec h.264 processor using verilog hdl. i request you to send video codec H.264 on Verilog hdl. regards D Ramana, M.Tech(Ph.D) SATHYABAMA